ASIC Engineering Technical Leader

The application window is expected to close on: 04/24/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact You are an experienced ASIC Technical Lead with a breadth of understanding of the full ASIC development flow including front-end and back-end processes. You possess the technical skills to directly contribute to front-end initiatives including Architecture, Design, Design Verification, Synthesis, Static Timing Analysis, Clock Domain Crossing analysis. Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency. Architect and design RTL subsystems and perform top-level IP integration. Mentor and coach early-in-career engineers in front-end ASIC development, driving continuous improvement in technical skills and execution. Perform Synthesis and Timing analysis including development of SDCs. Collaborate with the Physical Design team to verify timing and validate sufficient margin to insure manufacturability/yield. Collaborate with the DFT teams to meet testability requirements. Debug complex silicon and system-level issues during emulation and bring-up. Perform Post Silicon Validation and assess performance vs power trade-offs. Collaborate with the SW/SDK teams to implement the necessary system level features/APIs. Create full-chip clocking diagrams and related documentation. Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC or related experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC or related experience. Prior experience with block/subsystem RTL development. Prior experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus. Prior experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming. Preferred Qualifications Experience influencing design for testability and verification. Experience with power savings techniques and tools including clock gating, power gating and multi-voltage domains. Experience with Spyglass CDC and glitch analysis. Experience with emulation and prototyping platforms (Veloce, HAPS). Experience using Formal Verification: Synopsys Formality and Cadence LEC. Expertise in multiple protocols (PCIe, CXL, Ethernet, AXI, DDR, MMU, etc.). Experience with scripting languages such as Python, Perl, or TCL. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $149,100.00 to $218,900.00 and reflects the projec ... (truncated, view full listing at source)