Senior Hardware Engineer- FPGA

Cisco
Milpitas, California, US$152k – $222kPosted 4 March 2026

Tech Stack

Job Description

The application window is expected to close on: 02/30/26 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is an onsite role and will require working out of the Milpitas office location at least 4 days/week. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco’s core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio. Your Impact You will work on cutting edge, next generation routers powering AI buildout. You will be responsible for taking networking system requirements, mapping them into functional blocks for FPGA implementation, working with the cross functional team to address development requirements, participate in validation of the system, and release to manufacturing. You will work on the High-End Routing team that designs the ASR8000 routers. You will be a member of the FPGA team that designs control path FPGAs for the various boards. You will interface with Diagnostics, Software, Board design, Manufacturing and Hardware Qualification teams to ensure smooth delivery of the project. You are an experienced FPGA designer able to write RTL code, run simulations, address timing and other constraints, then generate programming files. You can work with many teams to resolve system level issues. In addition, you have good analytical skills and can deal with the complexity of System Hardware and Software interactions. You have a grasp of the system design for a router or line card and are also able to lead meetings, drive issues to resolution, and communicate clearly with all stakeholders. Minimum Qualifications Bachelor’s Degree in Electrical Engineering or relevant degree and 7+ years of related experience Or Master’s Degree in Electrical Engineering or relevant degree and 4+ years of related experience FPGA or ASIC development experience from specification to production. Experience with Verilog/System Verilog RTL coding Experience with industry leading FPGA devices and tools. Preferred Qualifications Experience with UVM and/or VMM Verification methodology. Experience with high-speed design debug. Experience with advanced microprocessor-based design. Low level networking card debug experience. Experience with CPU based peripherals architecture. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $152,400.00 to $221,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the ... (truncated, view full listing at source)
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