Senior ASIC Physical Design Engineer - Maynard, MA or Austin, TX

The application window is expected to close on: 03/13/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Join the Cisco Acacia Communications team in developing intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Acacia’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact As a Senior Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will: • Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) • Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies • Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools • Implement and manage timing ECO strategies • Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues related to design, tools, etc. • Evaluate and implement new timing methodologies; provide creative debugging solutions • Contribute to best practices and drive methodology alignment across projects Minimum Qualifications • Bachelors degree in Computer or Electrical Engineering and 7+ years of related experience, or Masters degree in Computer or Electrical Engineering and 4+ years of related experience • Hands-on experience in ASIC physical design and implementation • Experience with place & route using tools such as Cadence Innovus, Synopsys ICC2, or industry equivalent tools • Experience with industry standard CAD methodologies (Cadence, Synopsys, or Mentor) Preferred Qualifications • Experience with floor planning & partitioning, formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, EMIR • Experience with Static Timing Analysis including tools such as PrimeTime-DMSA or Tempus • Experience with Scripting using languages such as TCL, Perl, Python, etc. • Synthesis experience including Synopsys DC/FC • Formal Verification experience using tools such Synopsys Formality or Cadence LEC • Experience with Power Integrity including tools such as Apache Redhawk or Voltus • Physical Verification DRC/LVS experience including tools such as Synopsys ICV or Mentor Calibre Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $146,700.00 to $214,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Ca ... (truncated, view full listing at source)