Hardware Engineering Technical Leader
CiscoSan Jose, California, US$169k – $241kPosted 22 April 2026
Tech Stack
Job Description
The application window is expected to close on: 04/22/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This position is an onsite position in our San Jose, CA Office. NOTE: Job posting may be removed earlier if the position is filled or if enough applications are received. Meet the Team We are a team passionate about advancing hardware technology and design, focusing on complex, high-speed board development and innovative solutions. Our work environment fosters self-motivation, teamwork, and strong communication to drive impactful results. Our team consists of skilled engineers and designers experienced in hardware technologies such as power, clock, memory, CPU, FPGA, and various interfaces. We collaborate closely to bring up complex boards and develop schematic, PCB, and Verilog HDL/VHDL designs. We value continuous learning and encourage the use of scripting languages like Python and TCL (Tool Command Language) to enhance our workflows. Your Impact In this role, you will contribute to the design and bring-up of high-speed, multilayer boards, applying your expertise in schematic and PCB design as well as hardware description languages. Your work will support the development of cutting-edge technology solutions, and your proactive communication and teamwork will be essential to our success. Minimum Qualifications Bachelor's degree plus 8 years of related experience, or master’s degree plus 6 years of related experience, or PhD plus 3 years of related experience. Experience with complex high-speed board design and board bring-up. Experience in leading teams of both internal and external stakeholders to address and resolve performance and quality issues within large complex programs. Experience in mechanical design principles, including tolerance analysis, fabrication methods, materials, validation testing, and familiarity with SI principles. Preferred Qualifications Experience with common hardware technologies including power, clock, memory, CPU, FPGA, and a variety of interfaces. Experience with schematic, PCB, and Verilog HDL/VHDL design. Experience with scripting languages such as Python and Tcl (Tool Command Language. Experience with Ethernet protocol and switching is a plus. Track record of effective collaboration with senior-level stakeholders to identify business needs and opportunities and achieve strategic objectives. Strong self-motivation, teamwork, and communication skills. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $168,800.00 to $241,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in ... (truncated, view full listing at source)
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