ASIC Engineer
CiscoSan Jose, California, US$165k – $241kPosted 30 April 2026
Tech Stack
Job Description
The application window is expected to close on: 04/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Participate in and contribute to chip architecture definition and discussions. Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support our design methodology. Mentor junior engineers on performing project tasks and problem solving. Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures. Perform diagnostic and post silicon validation tests in the lab. Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience or .Master’s degree in Electrical or Computer engineering and 6+ years of ASIC Design experience. Verilog/System Verilog programming experience. Interactive and waveform debug experience. Experience resolving setup and hold timing violations with RTL modification. Experience developing micro-architecture solutions and RTL implementation. Preferred Qualifications Scripting experience (Python, Perl, TCL, shell programming). Good written and verbal communication skills. Experience with digital design principles and microarchitecture concepts such as buffering and scheduling architectures. Experience with design quality checks including CDC (Clock Domain Crossing) and Spyglass static analysis. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $165,000.00 to $241,400.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life ins ... (truncated, view full listing at source)
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