ASIC Engineer

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join the Physical Design CAD & Methodology Team—a highly skilled group at the core of ASIC implementation and signoff. Our team develops, maintains, and optimizes RTL-to-GDS Physical Design flows, enabling high-quality, scalable, and repeatable silicon execution across multiple programs. We work closely with Physical Design, STA, Power, Physical Verification, and Front-End teams to ensure robust methodologies, predictable QoR, and successful tape-outs. We are a collaborative, technically driven team that values clean design practices, automation, and continuous improvement. If you enjoy deep technical problem-solving, flow ownership, and influencing how chips get built, this is the team for you. Your Impact As a Physical Design Flow & Methodology Engineer, you will play a critical role in developing, maintaining, and optimizing block- and chip-level Physical Design implementation flows, from synthesis handoff through timing, power, and physical signoff.. You will collaborate with Physical Design engineers, STA, Power, and Physical Verification teams to enable consistent, high-quality PD execution across projects. You will own the setup, configuration, and maintenance of EDA tools and PD flows, troubleshoot complex convergence issues (timing, congestion, IR, DRC), and drive methodology improvements. You will develop and maintain flow automation, QA regression suites, and comprehensive documentation, ensuring that PD flows are robust, reusable, scalable, and signoff-ready. Your work will directly impact QoR, turnaround time, and tape-out success across multiple ASIC programs. Your contributions will directly impact project efficiency, quality, and the success of multiple ASIC designs. Minimum Qualifications Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field 3+ years of experience in at least one of the following: ASIC design, physical implementation, or CAD/flow engineering Hands-on experience with at least one major EDA tool (e.g., Fusion Compiler, PrimeTime, PrimePower, Innovus, Calibre, or ICV) Proficiency in at least one scripting language (Tcl, Python, or Shell) Strong understanding of digital design fundamentals, including RTL, synthesis, and physical design concepts Preferred Qualifications Experience developing or maintaining PD flow automation and methodology frameworks Familiarity with ASIC signoff collateral, including: Liberty (.lib), LEF/DEF, GDS; SDC, SPEF, SDF Understanding of multi-corner, multi-mode (MCMM) timing and signoff strategies Strong attention to detail with a focus on quality, reproducibility, scalability, and maintainability Ability to clearly document flows and communicate methodology concepts across teams Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Cisconians power the future. We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale. The depth and breadth of our technology doesn't just benefit our customers – it also means limitless opportunities for us to experiment and learn. We understand the power each of our unique backgrounds brin ... (truncated, view full listing at source)