ASIC Engineering Technical Leader

Meet the Team Join the Physical Design CAD & Methodology Team—a senior technical group responsible for defining, scaling, and sustaining RTL-to-GDS Physical Design implementation and signoff methodologies across complex ASIC programs. Our team partners closely with Physical Design, STA, Power, Physical Verification, Front-End, and Silicon Architecture teams to drive predictable QoR, fast convergence, and first-pass silicon success. We are a highly collaborative, execution-focused team that values deep technical expertise, ownership, and mentorship. If you are passionate about shaping how advanced chips are implemented and signed off, this is the team for you. Your Impact As a Physical Design Flow & Methodology Technical Leader, you will provide technical leadership in defining, developing, and maintaining scalable, signoff-robust Physical Design flows from synthesis handoff through final GDS delivery. You will work on PD methodologies, drive flow standardization, and lead complex debug efforts involving timing, power, congestion, and physical verification. You will partner with technical leads and program stakeholders to influence implementation strategy, tool usage, and signoff criteria. In this role, you will mentor engineers, review designs and flows, and lead methodology rollouts, flow migrations, and tool evaluations. You will work on flow QA infrastructure, regression strategies, and documentation, ensuring long-term scalability and maintainability. Your leadership will directly impact tape-out predictability, QoR consistency, and engineering productivity across multiple ASIC programs. Minimum Qualifications University degree in Electrical Engineering, Computer Engineering, or a related field and 8+ years of experience in ASIC Physical Design, PD flow/methodology, or CAD engineering Deep hands-on experience with Physical Design and signoff tools, such as: Fusion Compiler or Innovus; PrimeTime (MCMM STA); PrimePower or equivalent power analysis tools; Calibre or ICV for physical verification Expert-level understanding of RTL-to-GDS Physical Design and signoff flow, including synthesis handoff, ECOs, and tape-out requirements Strong proficiency in timing, power, and physical verification signoff methodologies Advanced proficiency in scripting and automation (Tcl, Python, Shell) Proven ability to lead complex cross-tool and cross-domain debug efforts Preferred Qualifications Demonstrated experience owning and evolving enterprise-scale PD flows Strong understanding of MCMM timing, power signoff, and SI-aware implementation Experience with power integrity signoff (static/dynamic IR drop, EM/EMIR) Familiarity with advanced process nodes and design rule complexity Experience leading methodology reviews, best-practice definitions, and technical training Excellent documentation skills and the ability to communicate complex methodology concepts clearly Track record of mentoring engineers and influencing technical direction across teams High attention to detail with a strong focus on quality, reproducibility, and long-term maintainability Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Cisconians power the future. We make impact as a team, innovatin ... (truncated, view full listing at source)