Physcial Design Engineer I (Full Time) - United States

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice.   Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.     Meet the Team   Cisco is well known for developing ground-breaking products in short time intervals. To support new product development at an exciting pace the Acacia PD team is challenged to design, develop, and build ASIC designs. The work is essential for supporting the increasing demands of hybrid work environments and ensuring reliable, high-capacity network connections. The engineers work with technologies that involve the latest submicron technologies. An ASIC PD engineer would be involved in developing and optimizing physical floorplan and their implementation.     Your Impact   The Physical Design Engineer Co-op will perform one or more of the following tasks while working on Cisco's elite optical communication products. The Co-op will be assigned relevant work assignments to challenge them according to their current level of experience and capability.     The Co-op may find themselves working in the following areas:   Work with Front-End teams to understand the design architecture to ensure optimal physical implementation   Gate level netlist synthesis (physical synthesis)   Physical implementation (floorplanning, placement, CTS, routing)   Power, performance and area optimization of design   Static Timing analysis and signoff closure   Physical verification and signoff closure   EMIR analysis and signoff closure     Minimum Qualifications   Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor’s degree program in computer science, electrical engineering, or related program   Must be able to be onsite in Maynard, MA two days a week   Knowledge of the design cycle from RTL to GDSII   Understanding of Static Timing Analysis, timing closure and design constraints   Knowledge in block level synthesis, place and route, timing closure, PnR and signoff tools and their capabilities     Preferred Qualifications   Interest in VLSI design, and more specifically in ASIC physical design and verification   Interest and preferably academic experience in deep submicron CMOS technologies   Scripting experience with perl, tcl, python and/or shell, a plus   Analytical and creative, with well-developed and tenacious problem-solving skills   Previous internship experience   Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share mo ... (truncated, view full listing at source)