Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid)

The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design methodology from conception to production. * You will collaborate with cross-functional teams from Testing, ATE, reliability, packaging, and hardware design team Minimum qualifications: * BSEE degree with 8+ years of experience or equivalent or an MS degree with 6+ years of experience, or equivalent or a PhD with 3+ years of experience, or equivalent * Design, simulation and measurement of high speed ICs experience in at least 3 areas below: High Speed Serial Links utilizing serializers, deserializers, and data convertors, voltage regulators, output drivers, phase locked loops, clock transmission/propagation, opamps, programmable gain amplifiers, and equalization Preferred qualifications: * Experience with electrical transceiver applications including backplane and cable communications * Experience with FinFET technology * High-frequency layout experience a plus: Passive component design: inductors, * transformers, transmission-lines, etc. * Floorplanning (power/ground, digital/analog signal routing, etc.) experience * Custom transistor layout experience * Experience designing for manufacturability * Experience with ESD laboratory practices and methodology * Experience with Cadence (virtuoso), Spectre/APS/SpectreX, Matlab, EMX * Experience with mixed-signal simulations in AMS Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $142,000.00 to $181,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay i ... (truncated, view full listing at source)