FPGA Design Engineer

<p><strong>Who You’ll Work With</strong></p><p>As a core member of the FPGA Design and Verification team, the candidate will be part of a fast-paced, high caliber team Designing and Verifying control path FPGA's for Arista Network products used in the computer networking industry's largest data centers. The FPGA Design Engineer is responsible for all aspects of the control path FPGA, from collecting the functional requirements that are needed, to reviewing the schematics of the board design engineer, to verifying the design using the latest tools, to bring-up and support of such a vital part of the networking hardware design. &#xa0;The successful candidate will work closely on a project from its early conception to the customer shipment and support when needed. They will work with fellow engineers and members of the hardware, software, and manufacturing team to understand the feature requirements, design and validate it. Besides closely working with the hardware engineers in designing the board, they will also review the hardware specifications and take ownership of the control path FPGA.&#xa0;</p><p><strong>What You’ll Do&#xa0;</strong></p><ul><li>Verilog/System Verilog code development, integration, simulation, and testbench creation &#xa0;</li><li>Perform FPGA implementation including synthesis, place and route, timing analysis, and debug&#xa0;</li><li>Collaborate with hardware and software engineers for rapid system-level bringup and debugging of network switch designs</li><li>Participate in fpga level code reviews, as well as schematic and board design reviews</li><li>Incorporate scripting to process input/output data for FPGA toolchains</li></ul><p><strong>Concepts and Skills You May Learn</strong></p><ul><li>Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc.</li><li>Protocols using Ethernet, such as PTP, SFlow, POE, etc.</li><li>Real world applications and the challenges of FPGA design, including resource/timing constraints, race conditions, state machines, etc.</li><li>Exposure to multiple FPGA vendor architectures, IDEs, and toolchains (Xilinx, Altera, Microsemi, etc.)</li><li>Simulation software for FPGA functional verification</li><li>How to read and interpret PCB schematics as they pertain to FPGA code development</li><li>Cross-functional collaboration to ideate and solve system-level technical challenges&#xa0;</li></ul> <ul><li>1-5 years of designing Verilog/System-Verilog RTL code</li><li>Control path design experience (Ethernet Data path design experience preferred)</li><li>On-chip bus interfacing design experience e.g. AXI (Streaming bus interfacing design experience preferred)</li><li>FPGA design resource and timing closure experience preferred</li><li>Python/TCL/Scripting experience</li></ul><p><strong>Compensation Information&#xa0;</strong></p><p>The new hire base pay for this role has a pay range of $110,000 to $170,000.&#xa0;</p><p>Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location.&#xa0;</p><p>The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location. &#xa0;</p><p>#LI-SP1</p> <div sr-tagline=""></div><p>Arista Networks is an equal opportunity employer.&#xa0; Arista makes all hiring and employment-related ... (truncated, view full listing at source)