Semiconductor IC Quality & Reliability Engineer

Cisco
2 Locations$141k – $183kPosted 13 March 2026

Job Description

The application window is expected to close on: 03/13/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Semiconductor IC Quality & Reliability Engineer Members of the Supply Chain organization at select locations will generally be expected to follow a hybrid work model, which includes two days of in-office attendance each week, with limited exceptions. Meet the Team Join Cisco's Semiconductor and Silicon Photonics Packaging team within the Component Quality and Technology Group to work on Quality and Reliability of analog/mixed-signal semiconductor ICs that go into our best-in-class Silicon Photonics products. Work alongside industry leaders in Quality, Reliability, Design, and Supply Chain, supporting innovation at the heart of Cisco's Optics portfolio. Your Impact Drive and influence quality and reliability assessments for semiconductor ICs, with a focus on analog/mixed-signal custom ASICs designed for Cisco silicon photonic products. Develop and manage (die and package) qualification strategies to ensure products meet JEDEC reliability standards and Cisco’s quality requirements. Lead cross-functional failure analysis, problem-solving, and support detailed debug activities to resolve and prevent issues. Deliver clear qualification reports and summaries to internal stakeholders and key customers Collaborate with suppliers and engineering partners and plan reliability qualification execution for new product releases and ongoing monitoring. Review and qualify changes from semiconductor PCNs, analyze EOL/LTB notices, and collaborate with Design and Supply Chain teams to ensure reliable sourcing. Minimum Qualifications: BS/MS in Electrical Engineering, Electronics, or a related field 3+ years of experience in semiconductor quality and reliability, or a similar role Working knowledge of analog/mixed signal ICs used in high-speed optical transceivers Familiarity with JEDEC reliability standards and industry best practices Preferred Qualifications Expertise in reviewing and defining design, qualification and reliability requirements for ASICs, FPGAs, and semiconductor components Solid understanding of semiconductor manufacturing, IC test methodologies, and common silicon and package failure mechanisms is highly desirable Ability to interpret complex datasheets and technical documents Strong communication skills and ability to thrive in a collaborative, fast-paced environment Familiarity implementing machine learning (ML) or artificial intelligence (AI) methods with engineering workflows Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $140,800.00 to $183,000.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For lo ... (truncated, view full listing at source)
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