SOC Micro-architecture & RTL Design Lead (Manager)

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems, including hardware and software, to train and run the largest ML workloads for AGI. MatX is seeking a SOC Micro-architecture and RTL Design Lead (Manager) to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for leading a team of micro-architects and RTL designers at MatX in delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies. What You'll Do Here At least 5 years of experience leading a team of micro-architects and RTL designers responsible for subsystems and chip-level design of MatX silicon Hire and manage team members to create and retain a world-class silicon design team Co-own the development of MatX silicon with other functional leads across silicon, software, system design, and ML Oversee the delivery of completed micro-architecture and completed frontend RTL designs to downstream teams for siliconization, including verification, physical design, DFT, etc Co-own the flow for handoffs to and from stakeholder teams to the RTL design team Co-own the process for IP selection and vendor selection for silicon-related IPs, tools, and partners for various aspects of silicon development Work with executive management on planning for hiring and operational budgeting to provide all necessary tools and IPs for MatX silicon development Conduct technical reviews within the team you lead, as well as cross-functionally Who You Are Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon Experience in creating and managing teams for RTL design and/or related silicon areas Demonstrated track record of working in fast-paced, cross-matrixed organizations that require matrixed co-ownership of the development of complex silicon and related software and system products Ability to jump into RTL design and micro-architecture hands-on if required, and to be able to technically review and debate these aspects with the team as a highly technical manager Hands-on experience with SystemVerilog, Python, C/C++, Bluespec, and similar scripting and programming languages for chip design and related flows Production-proven experience in leadership as well as technical delivery for silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related functionalities This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week, on Tuesday through Thursday Bonus Points If You Have A huge plus if you have experience in a similar role in a startup environment, as well as a larger organization A big plus if you have experience in a similar role in a startup environment What We Offer A Stake in our success A cash/equity mix that fits your needs and option to do early exercise Health Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t) Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood Learning Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities Team Connection Team Lunches, quarterly off-sites, and regular town halls Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t! Flexible Spending Accounts Pre-tax spend accounts for medical, dental/visio ... (truncated, view full listing at source)