DVT Engineer (Board + System Validation)

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p class="p1"><strong>Role Summary:</strong></p> <p class="p2">We are looking for a hands-on DVT Engineer to execute Design Validation Test (DVT) at both the board/subassembly level and the system level, working closely with a Principal DVT Technical Lead. You will help build repeatable test setups, execute validation plans, debug failures, and drive issues to closure with cross-functional design teams. The work spans high-power power-delivery hardware, high-speed I/O, and complex electro-mechanical systems (thermal/cooling/optics interfaces).</p> <p class="p3"><strong>What You’ll Work On:</strong></p> <p class="p4"><strong>Board / Subassembly DVT</strong></p> <ul class="ul1"> <li class="li5">Execute bring-up and validation for complex PCBAs and subassemblies using documented test plans and procedures.</li> <li class="li5">Validate power-up/down sequences and power delivery behavior, including DC IR drop and AC noise/ripple characterization and rail margining.</li> <li class="li5">Validate clocking and high-speed I/O links at the board and interconnect level (connectors/cables), and assist with SI-related debug.</li> <li class="li5">Validate low-speed management interfaces (e.g., I2C/SPI/USB) and contribute to debugging intermittent/systemic failures.</li> <li class="li5">Run stress testing (extended runtime, temperature cycling) and document results with clear pass/fail and anomaly notes.</li> </ul> <p class="p4"><strong>System-Level DVT</strong></p> <ul class="ul1"> <li class="li5">Support DVT execution in lab and chamber environments, including setup, instrumentation, and day-to-day test operations.</li> <li class="li5">Execute and triage system-level test failures; gather data, isolate suspects, and work with the Principal DVT Lead to drive RCAs.</li> <li class="li5">Support validation that spans electrical + mechanical + thermal interactions (e.g., cooling loop behavior, thermal limits, optics/power interactions).</li> <li class="li2">Assist with integrating diagnostics/software hooks into DVT workflows (logging, scripts, data capture) to improve throughput and repeatability.</li> </ul> <p class="p3"><strong>Key Responsibilities:</strong></p> <p class="p4"><strong>Test Execution Lab Ownership</strong></p> <ul class="ul1"> <li class="li5">Build and maintain benchtop and rack-level test setups (instrumentation, cabling, fixtures) to enable repeatable validation runs.</li> <li class="li5">Execute unit, subassembly, and system tests; capture data and logs; summarize results in concise reports and bug write ... (truncated, view full listing at source)