DVT- Technical Lead

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p class="p1"><strong>Role Summary</strong></p> <p class="p2">We are seeking a hands‑on DVT Technical Lead (Individual Contributor) to own and drive the Design Validation Test (DVT) process end‑to‑end across complex electrical engineering boards and full systems. You will define validation strategy, build test plans and infrastructure, lead deep debug and root‑cause analysis (RCA), and drive closure through design changes and re‑test. The domain includes difficult power delivery technology, fast high‑speed I/O, and electro‑mechanical systems with thermal, optics, and high‑power constraints. People management is not required (mentoring is a plus).</p> <p class="p3"><strong>What You’ll Own</strong></p> <p class="p4"><strong>1) Board / Subassembly DVT (EE-heavy)</strong></p> <ul class="ul1"> <li class="li5">Own DVT for complex PCBAs and subassemblies from first power‑on through design sign‑off.</li> <li class="li5">Power validation: power‑up/down sequencing, regulator/hotswap behavior, rail margining, DC IR drop, and AC noise/ripple characterization.</li> <li class="li5">Clock distribution validation and high‑speed I/O interface validation (e.g., Ethernet/PCIe-class links, board‑to‑board connectors and cabling).</li> <li class="li5">Low‑speed system management interface validation (e.g., I2C/SPI/USB) and debug of intermittent or systemic failures.</li> <li class="li5">Stress/environmental testing (extended runtime, temperature cycling) and characterization under margined conditions.</li> </ul> <p class="p4"><strong>2) System-level DVT (integration + electro-mechanical)</strong></p> <ul class="ul1"> <li class="li5">Own system integration validation planning and execution across representative configurations and operating envelopes.</li> <li class="li5">Drive readiness and execution across lab and chamber environments, including dependency management (test scripts, instrumentation, SW readiness, sample availability).</li> <li class="li5">Validate and debug system-level issues spanning electrical, mechanical, thermal, and optics interactions.</li> <li class="li2">Partner with reliability and manufacturing teams to ensure DVT coverage supports ramp readiness and reduces escapes.</li> </ul> <p class="p3"><strong>Key Responsibilities</strong></p> <p class="p4"><strong>DVT Strategy, Plans, and Coverage</strong></p> <ul class="ul1"> <li class="li5">Define a risk‑based DVT strategy spanning board/subassembly engineering validation through system integration validation.</li> <li class="li5">Author and maintain DVT plans ... (truncated, view full listing at source)